1. Field of the Invention:
The present invention relates to a horizontal charge transfer register for use in a CCD (Charge-Coupled-Device) solid-state imaging device or the like.
2. Description of the Prior Art:
FIGS. 1 and 2 of the accompanying drawings show final and output stages of a conventional horizontal charge transfer register in a CCD solid-state imaging device. As shown in FIG. 1, the horizontal charge transfer register, generally denoted at 1, has an array of charge transfer sections 3 each having charge transfer electrodes, i.e., a charge storage electrode 2S and a charge transfer electrode 2T. The charge transfer sections 3 horizontally transfer signal charges in response to two-phase drive pulses .phi.H.sub.1, .phi.H.sub.2. The final charge transfer section 3 is supplied with an independent drive pulse .phi.H.sub.1 that is larger in amplitude than those drive pulses .phi.H.sub.1, .phi.H.sub.2 which are applied to the charge transfer sections 3 that precede the final charge transfer section 3. The horizontal charge transfer register 1 also includes an embedded channel region 4 serving as a charge transfer path, and a channel stop region 5 in an output section 9. The final charge transfer section 3 of the horizontal charge transfer register I is connected to a floating diffusion region 7 in the output section 9 through a horizontal output gate section 6 to which a gate voltage V.sub.HOG is applied. Signal charges from the horizontal charge transfer register 1 are transferred through the horizontal output gate section 6 to the floating diffusion region 7 by which the signal charges are converted into a voltage that is outputted through an output amplifier 8. The output section 9 also includes a reset gate section 11 for discharging signal charges, which have been transferred to the floating diffusion region 7, into a reset drain region 10 in response to a gate voltage .phi.RG applied to the reset gate section 11 between the floating diffusion region 7 and the reset drain region 10.
As shown in FIG. 2, which is a cross-sectional view taken along line II--II of FIG. 1, a P-type well region 14 is formed on an N-type semiconductor substrate 13, and the embedded channel region 4, which is of the N type, as the charge transfer path of the horizontal charge transfer register 1 is formed in the P-type well region 14. The charge storage and transfer electrodes 2S, 2T are alternately deposited on the N-type embedded channel region 4 with an insulative film 15 interposed therebetween. The charge storage and transfer electrodes 2S, 2T are connected in pairs, providing the array of charge transfer sections 3 to which two-phase drive pulses .phi.H.sub.1, .phi.H.sub.2 will be applied. P.sup.- layers 16 for developing a potential difference are disposed in the N-type embedded channel region 4 beneath the charge transfer electrodes 2T, respectively.
The horizontal output gate section 6 comprises a horizontal output gate electrode 17 deposited on the insulative film 15 on the embedded channel region 4. The gate voltage V.sub.HOG is applied to the horizontal output gate electrode 17. Both the floating diffusion region 7 and the reset drain region 10 are in the form of an N.sup.+ layer. The reset gate section 11 comprises a reset gate electrode 18 deposited on the insulative film 15 on the N-type region between the regions 7, 10.
In order to increase the gain of a so-called floating diffusion amplifier including the floating diffusion region 7 and the output amplifier 8, the charge transfer path or the embedded channel region 4 beneath the horizontal output gate section 6 is tapered or constricted such that the width W.sub.1 thereof is progressively smaller from the final charge transfer section 3 toward the floating diffusion region 7.
As described above, in the conventional horizontal charge transfer register 1, the width W.sub.1 of the embedded channel region 4 beneath the horizontal output gate section 6 is progressively smaller from the final charge transfer section 3 toward the floating diffusion region 7. Therefore, the electric field of the horizontal output gate section 6 acts in a direction b that is opposite to a direction a in which signal charges are transferred, under the influence of the electric field of the surrounding P.sup.+ channel stop region 5. This is because the electric field of a portion of the horizontal output gate section 6 near the floating diffusion region 7 is modulated as it is strongly affected by the electric field of the channel stop region 5 because of the reduced width W.sub.1 of the portion near the floating diffusion region 7, and the potential in that portion is lower than that in a portion of the horizontal output gate section 6 whose width W.sub.1 is larger (see a solid-line curve 19 in the potential diagram of FIG. 8 of the accompanying drawings). As a result, the charge transfer efficiency of the horizontal output gate section 6 is relatively low.
Furthermore, since signal charges that have sufficiently been spread transversely across the horizontal charge transfer register 1 are collected into the horizontal output gate section 6, those signal charges which are positioned in transverse ends of the horizontal charge transfer register 1 have to travel a distance larger than those signal charges which are positioned in the center of the horizontal charge transfer register 1. The different distances to be traversed by the signal charges also adversely affect the charge transfer efficiency.